On-chip crosstalk noise reduction model using interconnect optimization techniques

Abstract

This paper presents an improved crosstalk 2n model for noise constrained interconnects optimization. The proposed model has simple closed-form expressions, which is capable of predicting the noise amplitude and the noise pulse width of an RC interconnect as well as coupling locations (near-driver and near-receiver) on victim net. This is efficient and sufficiently accurate to be effectively incorporated in state-of-the-art noise calculators(less than 6% error on average compared with HSPICE simulator In particularly we demonstrate its effectiveness in the following application: Optimization rule generation for noise reduction using various interconnects optimization techniques. ©2008 IEEE.