Please use this identifier to cite or link to this item: http://gukir.inflibnet.ac.in:8080/jspui/handle/123456789/3700
Title: On-chip crosstalk noise reduction model using interconnect optimization techniques
Authors: Hunagund P.V
Kalpana A.B.
Issue Date: 2008
Citation: IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE , Vol. , , p. 87 - 91
Abstract: This paper presents an improved crosstalk 2n model for noise constrained interconnects optimization. The proposed model has simple closed-form expressions, which is capable of predicting the noise amplitude and the noise pulse width of an RC interconnect as well as coupling locations (near-driver and near-receiver) on victim net. This is efficient and sufficiently accurate to be effectively incorporated in state-of-the-art noise calculators(less than 6% error on average compared with HSPICE simulator In particularly we demonstrate its effectiveness in the following application: Optimization rule generation for noise reduction using various interconnects optimization techniques. ©2008 IEEE.
URI: 10.1109/SMELEC.2008.4770282
http://gukir.inflibnet.ac.in:8080/jspui/handle/123456789/3700
Appears in Collections:2. Conference Papers

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